Z80 Instruction Set Summary
Written by Jonathan Bowen

       ----------------------------------------------------------------
       |                                                              |
       |                                                              |
       |                            Zilog                             |
       |                                                              |
       |                 ZZZZZZZ    88888      000                    |
       |                      Z    8     8    0   0                   |
       |                     Z     8     8   0   0 0                  |
       |                    Z       88888    0  0  0                  |
       |                   Z       8     8   0 0   0                  |
       |                  Z        8     8    0   0                   |
       |                 ZZZZZZZ    88888      000                    |
       |                                                              |
       |          Z80 MICROPROCESSOR Instruction Set Summary          |
       |                                                              |
       |                                                              |
       |Written by     Jonathan Bowen                                 |
       |               Programming Research Group                     |
       |               Oxford University Computing Laboratory         |
       |               8-11 Keble Road                                |
       |               Oxford OX1 3QD                                 |
       |               England                                        |
       |                                                              |
       |               Tel +44-865-273840                             |
       |                                                              |
       |Created        August 1981                                    |
       |Updated        April 1985                                     |
       |Modified       by Robert Taylor on 27/12/95 for compatibilty  |
       |               with TASM                                      |
       |Issue          1.3                Copyright (C) J.P.Bowen 1985|
       ----------------------------------------------------------------
 
    Click to return
to the site's menu... or here to get back to the tutorial's menu.
Mnemonic SZHPNC Description Notes
ADC A,s
ADC HL,ss
ADD A,s
ADD HL,ss
ADD IX,pp
ADD IY,rr
AND s
BIT b,m
CALL cc,nn
CALL nn
CCF
CP s
CPD
CPDR
CPI
CPIR
CPL
DAA
DEC s
DEC xx
DEC ss
DI
DJNZ e
EI
EX (SP),HL
EX (SP),xx
EX AF,AF'
EX DE,HL
EXX
HALT
IM n
IN A,(n)
IN r,(C)
INC r
INC (HL)
INC xx
INC (xx+d)
INC ss
IND
INDR
INI
INIR
JP (HL)
JP (xx)
JP nn
JP cc,nn
JR e
JR cc,e
LD dst,src
LD A,i
LDD
LDDR
LDI
LDIR
NEG
NOP
OR s
OTDR
OTIR
OUT (C),r
OUT (n),A
OUTD
OUTI
POP xx
POP qq
PUSH xx
PUSH qq
RES b,m
RET
RET cc
RETI
RETN
RL m
RLA
RLC m
RLCA
***V0*
**?V0*
***V0*
--?-0*
--?-0*
--?-0*
***P00
***P00
------
------
--?-0*
***V1*
****1-
****1-
****1-
****1-
--1-1-
***P-*
***V1-
------
------
------
------
------
------
------
------
------
------
------
------
------
***P0-
***V0-
***V0-
------
***V0-
------
?*??1-
?1??1-
?*??1-
?1??1-
------
------
------
------
------
------
------
**0*0-
--0*0-
--000-
--0*0-
--000-
***V1*
------
***P00
?1??1-
?1??1-
------
------
?*??1-
?*??1-
------
------
------
------
------
------
------
------
------
**0P0*
--0-0*
**0P0*
--0-0*
Add with Carry
Add with Carry
Add
Add
Add
Add
Logical AND
Test Bit
Conditional Call
Unconditional Call
Complement Carry Flag
Compare
Compare and Decrement
Compare, Dec., Repeat
Compare and Increment
Compare, Inc., Repeat
Complement
Decimal Adjust Acc.
Decrement
Decrement
Decrement
Disable Interrupts
Dec., Jump Non-Zero
Enable Interrupts
Exchange
Exchange
Exchange
Exchange
Exchange
Halt
Interrupt Mode
Input
Input
Increment
Increment
Increment
Increment
Increment
Input and Decrement
Input, Dec., Repeat
Input and Increment
Input, Inc., Repeat
Unconditional Jump
Unconditional Jump
Unconditional Jump
Conditional Jump
Unconditional Jump
Conditional Jump
Load
Load
Load and Decrement
Load, Dec., Repeat
Load and Increment
Load, Inc., Repeat
Negate
No Operation
Logical inclusive OR
Output, Dec., Repeat
Output, Inc., Repeat
Output
Output
Output and Decrement
Output and Increment
Pop
Pop
Push
Push
Reset bit
Return
Conditional Return
Return from Interrupt
Return from NMI
Rotate Left
Rotate Left Acc.
Rotate Left Circular
Rotate Left Circular
A=A+s+CY
HL=HL+ss+CY
A=A+s
HL=HL+ss
IX=IX+pp
IY=IY+rr
A=A&s
m&{2^b}
If cc CALL
-(SP)=PC,PC=nn
CY=~CY
A-s
A-(HL),HL=HL-1,BC=BC-1
CPD till A=(HL)or BC=0
A-(HL),HL=HL+1,BC=BC-1
CPI till A=(HL)or BC=0
A=~A
A=BCD format
s=s-1
xx=xx-1
ss=ss-1

B=B-1 till B=0

(SP)<->HL
(SP)<->xx
AF<->AF'
DE<->HL
qq<->qq' (except AF)

(n=0,1,2)
A=(n)
r=(C)
r=r+1
(HL)=(HL)+1
xx=xx+1
(xx+d)=(xx+d)+1
ss=ss+1
(HL)=(C),HL=HL-1,B=B-1
IND till B=0
(HL)=(C),HL=HL+1,B=B-1
INI till B=0
PC=(HL)
PC=(xx)
PC=nn
If cc JP
PC=PC+e
If cc JR(cc=C,NC,NZ,Z)
dst=src
A=i (i=I,R)
(DE)=(HL),HL=HL-1,#
LDD till BC=0
(DE)=(HL),HL=HL+1,#
LDI till BC=0
A=-A

A=Avs
OUTD till B=0
OUTI till B=0
(C)=r
(n)=A
(C)=(HL),HL=HL-1,B=B-1
(C)=(HL),HL=HL+1,B=B-1
xx=(SP)+
qq=(SP)+
-(SP)=xx
-(SP)=qq
m=m&{~2^b}
PC=(SP)+
If cc RET
PC=(SP)+
PC=(SP)+
m={CY,m}<-
A={CY,A}<-
m=m<-
A=A<-
       
Mnemonic SZHPNC Description Notes
RLD
RR m
RRA
RRC m
RRCA
RRD
RST p
SBC A,s
SBC HL,ss
SCF
SET b,m
SLA m
SRA m
SRL m
SUB s
XOR s
**0P0-
**0P0*
--0-0*
**0P0*
--0-0*
**0P0-
------
***V1*
**?V1*
--0-01
------
**0P0*
**0P0*
**0P0*
***V1*
***P00
Rotate Left 4 bits
Rotate Right
Rotate Right Acc.
Rotate Right Circular
Rotate Right Circular
Rotate Right 4 bits
Restart
Subtract with Carry
Subtract with Carry
Set Carry Flag
Set bit
Shift Left Arithmetic
Shift Right Arith.
Shift Right Logical
Subtract
Logical Exclusive OR
{A,(HL)}={A,(HL)}<- ##
m=->{CY,m}
A=->{CY,A}
m=->m
A=->A
{A,(HL)}=->{A,(HL)} ##
 (p=0H,8H,10H,...,38H)
A=A-s-CY
HL=HL-ss-CY
CY=1
m=mv{2^b}
m=m*2
m=m/2
m=->{0,m,CY}
A=A-s
A=Axs
F
S
Z
HC
P/V
N
CY
-*01?
S
 Z
  H
   P
    N
     C
Flag unaffected/affected/reset/set/unknown
Sign flag (Bit 7)
Zero flag (Bit 6)
Half Carry flag (Bit 4)
Parity/Overflow flag (Bit 2, V=overflow)
Add/Subtract flag (Bit 1)
Carry flag (Bit 0)
n
nn
e
(nn)
(xx+d)
r
(rr)

b
p
Immediate addressing
Immediate extended addressing
Relative addressing (PC=PC+2+offset)
Extended addressing
Indexed addressing
Register addressing
Register indirect addressing
Implied addressing
Bit addressing
Modified page zero addressing (see RST)
DEFB n(,...)
DEFB 'str'(,...)
DEFS nn
DEFW nn(,...)
Define Byte(s)
Define Byte ASCII string(s)
Define Storage Block
Define Word(s)
A B C D E
AF BC DE HL
F
I
IX IY
PC
R
SP
Registers (8-bit)
Register pairs (16-bit)
Flag register (8-bit)
Interrupt page address register (8-bit)
Index registers (16-bit)
Program Counter register (16-bit)
Memory Refresh register
Stack Pointer register (16-bit)
b
cc
d
dst
e
m
n
nn
pp
qq
qq'
r
rr
s
src
ss
xx
One bit (0 to 7)
Condition (C,M,NC,NZ,P,PE,PO,Z)
One-byte expression (-128 to +127)
Destination s, ss, (BC), (DE), (HL), (nn)
One-byte expression (-126 to +129)
Any register r, (HL) or (xx+d)
One-byte expression (0 to 255)
Two-byte expression (0 to 65535)
Register pair BC, DE, IX or SP
Register pair AF, BC, DE or HL
Alternative register pair AF, BC, DE or HL
Register A, B, C, D, E, H or L
Register pair BC, DE, IY or SP
Any register r, value n, (HL) or (xx+d)
Source s, ss, (BC), (DE), (HL), nn, (nn)
Register pair BC, DE, HL or SP
Index register IX or IY
+ - * / ^
& ~ v x
<- ->
( )
( )+ -( )
{ }
#
##
Add/subtract/multiply/divide/exponent
Logical AND/NOT/inclusive OR/exclusive OR
Rotate left/right
Indirect addressing
Indirect addressing auto-increment/decrement
Combination of operands
Also BC=BC-1,DE=DE-1
Only lower 4 bits of accumulator A used